? semiconductor components industries, llc, 2001 may, 2001 rev. 5 1 publication order number: mc74ac4040/d mc74ac4040 12-stage binary ripple counter the mc74ac4040 consists of 12 master-slave flip-flops. the output of each flip-flop feeds the next and the frequency at each output is half that of the preceding one. the state of the counter advances on the negative-going edge of the clock input. reset is asynchronous and active-high. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and may have to be gated with the clock of the mc74ac4040 for some designs. ? 140 mhz typ. clock ? outputs source/sink 24 ma ? operating voltage range: 2.0 to 6.0 v ? high noise immunity 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 q11 q10 q8 q9 reset clk q1 q12 q6 q5 q7 q4 q3 q2 gnd figure 1. pinout: 16lead packages conductors (top view) function table clock reset output state l no change l advance to next state x h all outputs are low http://onsemi.com dip16 n suffix case 648 1 16 so16 d suffix case 751b 1 16 tssop16 dt suffix case 948f 1 16 see general marking information in the device marking section on page 4 of this data sheet. device marking information 1 16 eiaj16 m suffix case 966 device package shipping ordering information mc74ac4040n pdip16 25 units/rail mc74ac4040d soic16 48 units/rail mc74ac4040dr2 2500 tape & reel mc74ac4040dt tssop16 96 units/rail mc74ac4040dtr2 tssop16 soic16 2500 tape & reel mc74ac4040m eiaj16 50 units/rail
mc74ac4040 http://onsemi.com 2 figure 2. logic diagram clock 10 11 reset pin 16 = v cc pin 8 = gnd 9 7 6 5 3 2 4 13 12 14 15 1 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 maximum ratings* symbol parameter value unit v cc dc supply voltage (referenced to gnd) 0.5 to +7.0 v v in dc input voltage (referenced to gnd) 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma p d power dissipation in still air plastic soic package 750 500 mw t stg storage temperature 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c *maximum ratings are those values beyond which damage to the device may occur. 2derating: plastic dip: 10mw/ c from 65 c to 125 c soic package: 7.0 mw/ c from 65 c to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in /v out input voltage, output voltage (ref. to gnd) 0 v cc t a operating temperature, all package types 40 +85 c t r /t f input rise/fall time v cc = 3.0 v 0 150 ns/v t r /t f in ut rise/fall time (figure 1) v cc = 3 . 0 v v cc = 4.5 v 0 0 150 40 ns/v (figure 1) v cc 4.5 v v cc = 5.5 v 0 0 40 25
mc74ac4040 http://onsemi.com 3 dc characteristics (unless otherwise specified) symbol parameter value unit v in = v cc or gnd i cc maximum quiescent supply voltage 80 m a v cc = 5.5 v, cc a u qu esce su y o age 80 m t a = worst case v in = v cc or gnd i cc maximum quiescent supply current 8.0 m a v cc = 5.5 v, cc a u qu esce su y cu e 80 m t a = 25 c dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 2.1 2.1 v out = 0.1 v ugee input voltage 4.5 3.15 3.15 v or v cc 0.1 v 5.5 3.85 3.85 v il maximum low level 3.0 0.9 0.9 v out = 0.1 v au oee input voltage 4.5 1.35 1.35 v or v cc 0.1 v 5.5 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = 50 m a ugee output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 2.56 2.46 v 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 m a au oee output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 0.36 0.44 v 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 24 ma i in maximum input 55 01 10 m a v i =v cc gnd au u leakage current 5.5 0.1 1.0 m a v i = v cc , gnd i old minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time.
mc74ac4040 http://onsemi.com 4 ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f max maximum clock 3.3 110 120 100 mhz f max frequency 5.0 130 140 120 mh z n cp to q1 propagation delay 3.3 2.0 11 2.0 14 ns n cp to q 1 n cp to q1 5.0 2.0 8.0 2.0 10 ns q n to q n +1 propagation delay 3.3 0 5.5 0 6.5 ns q n to q n +1 q n to q n +1 5.0 0 3.5 0 4.5 ns mr to q propagation delay 3.3 3.0 12 3.0 15 ns oq t hl mr to q 5.0 3.0 10 3.0 12 ns t rec recovery time 3.3 0 2.5 0 ns rec n cp to mr r ecovery ti me 5.0 0 1.5 0 ns t w n cp minimum pulse width 3.3 4.0 3.5 4.5 ns t w n cp uused clock pin 5.0 3.0 2.5 3.5 ns t w mr minimum pulse width 3.3 4.0 3.5 4.5 ns t w mr uused master reset 3.0 3.0 2.5 3.5 ns *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week ac4040 awlyww mc74ac4040n awlyyww ac 4040 alyw dip16 so16 tssop16 eiaj16 74ac4040 alyw
mc74ac4040 http://onsemi.com 5 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip16 n suffix 16 pin plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 so16 d suffix 16 pin plastic soic package case 751b05 issue j
mc74ac4040 http://onsemi.com 6 package dimensions tssop16 dt suffix 16 pin plastic tssop package case948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n eiaj16 m suffix 16 pin plastic eiaj package case96601 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z
mc74ac4040 http://onsemi.com 7 notes
mc74ac4040 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74ac4040/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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